1. Field of the Invention
This invention relates to the field of semiconductor processing and, more particularly, to a method and apparatus which compensates for spatial variations in semiconductor processes by using non-uniform ion implantation distribution profiles across the wafer surface.
2. Description of Relevant Art
The manufacturing of integrated circuits involves the physical and chemical processing of semiconductor wafers, typically silicon wafers. The processing of wafers can involve the introduction of external species (either by diffusion or implantation) into the substrate, patterning using photolithography techniques, removing material using wet or dry etching, polishing using mechanical and/or chemical means, chemical and/or physical vapor depositing or growing of films, as well as other physical and chemical processes.
Each wafer is subdivided into several sites, called die, their number depending on the size of each die and the size of the wafer. The different die or "chips" can be microprocessors, SRAMs, DRAMs, flash memories, and other forms of integrated circuits. In the past 25 years, the diameter of silicon wafers has steadily increased from less than 1 in to 8 in (200 mm) diameter wafers which are currently used by many semiconductor manufacturing companies.
Throughout the history of semiconductor wafer processing, a challenge has been to develop physical and chemical processes that produce uniform results across the entire surface of the wafer. The increasing wafer diameter has made the task of producing uniform results even more challenging. The silicon wafers themselves start out having spatial variations. Single-crystalline silicon is grown from melts of electronic grade poly-crystalline silicon ("EGS") containing minute quantities of impurities. EGS is produced by processing and purifying raw silicon. As the crystal is gradually pulled out of the melt, it grows, expands, and cools in a single ingot which has spatial variations in the dopant levels. These variations can be from end-to-end of the cylindrical ingot due to depletion of the dopant from the molten pool during the pull, and/or the variations can extend radially outward from the center of the cylindrical ingot. The ingot is then sliced into thin wafers which may exhibit chemical, mechanical, and electrical disparity from wafer to wafer and radially across each wafer.
Subsequent processing, like doping and etching, on ingot slices (or wafers) was initially performed on groups of wafers called wafer "runs". For example, for wet etching, a cassette containing several wafers would be submerged into an acid bath or for thermal annealing, a cassette containing several wafers would be introduced into large furnaces. In most cases of group processing, the wafers would exhibit variations in chemical, mechanical, and electrical parameters from wafer to wafer and across each wafer. As the diameter of the wafers increased, more processing tools were developed to process only single wafers at a time. Individual wafer processing reduced variations from wafer to wafer by varying processing parameters from one wafer to another to compensate for initial parameter variability. Process volume was reduced and each wafer experienced exactly the same gas flows, temperatures, etc. In large diffusion furnaces, there are temperature variations front-to-back and depletion effects front-to-back.
However, radial or cross-wafer variability (i.e., spatial variation) remained. With the reduction of critical dimensions into the submicron level, spatial uniformity of processes across each wafer became even more critical since devices made with submicron critical dimensions demonstrate reduced tolerance to process non-uniformity.
Initial circuit design assumes that semiconductor processes produce uniform results across the entire wafer topography. The design of an integrated circuit is optimized only if uniform mechanical, chemical, and electrical parameters exist across a wafer. These design parameters may be, for example, threshold voltage, breakdown voltage, current consumption, and switching speed. However, since most semiconductor processes produce non-uniform results across the wafer topography, some of the design parameters may be outside the acceptable design limits in certain portions of the wafer. For small spatial variations in the semiconductor processes, the design parameters may be outside the acceptable design limits but the devices may still function. As the variations grow though, the devices may not function at all. Yield losses which are a result of spatial variations in the manufacturing processes are a significant problem in integrated circuit manufacturing.
It would thus be desirable to have a method and equipment that can first accurately measure and determine spatial variations across the wafer due to the manufacturing processes. The method and equipment should then be able to compensate for these spatial variations. Such a method and equipment should result in design parameters which are within the acceptable design limits, or as close as possible to an optimum value, not only within a region of the wafer but across the entire wafer topography.